A printed circuit board starts as a sheet of copper-clad laminate and ends as a tested interconnect. Between those two points the board is drilled, plated, imaged, etched, laminated, masked and finished — and each of those stages has a tolerance that constrains what you can design. Most manufacturability questions are decided in the first three stages, long before anyone looks at a solder-mask colour.
1. Inner layers are imaged and etched first
On a multilayer board the inner copper layers are imaged and etched before anything is laminated, so their line width and spacing are set at that point and cannot be recovered later. Registration — whether layer 3's features land on top of layer 5's — then depends on how accurately the stack is aligned during lamination and how much the prepreg moves as it cures. Above eight layers we use X-ray drill targeting after lamination specifically because mechanical registration alone is no longer good enough.
2. The drill determines the plating
A via is a hole with copper plated through it, and the plating has to reach the middle of the hole. The ratio of board thickness to drill diameter — the aspect ratio — governs how hard that is: at 8:1 it is routine, at 20:1 the plating solution circulates poorly and the barrel thins in the centre, and at 25:1 the process has to be run deliberately slowly and checked by cross-section. This is why a 3.2 mm board with 0.2 mm vias costs materially more than a 1.6 mm board with the same vias.
3. Etch tolerance is the hidden variable
Etching removes copper sideways as well as downwards. On 1 oz copper this undercut is small; on 6 oz it is not, which is why heavy copper boards need either a wider nominal trace or a stepped etch to hold the width. The figure we publish — ±8 µm trace-width accuracy — is what holds across our standard process window; it is not a guarantee on an arbitrary 13 oz inner layer.
4. Lamination fixes the geometry
Layers are stacked with prepreg between them and pressed under heat and vacuum until the resin cures. After lamination the board's thickness, dielectric heights and layer-to-layer registration are fixed. A stackup that looked fine on paper can warp here if copper distribution is asymmetric across the panel — which is why balanced copper is checked at DFM, not discovered at assembly.
5. Outer layers, mask and finish
Outer layers are imaged and plated after lamination, then the solder mask is applied over bare copper everywhere except the pads. Surface finish — ENIG, HASL, OSP and the rest — is applied last to keep the pads solderable. Each finish trades solderability, flatness and shelf life differently; the choice is assembly-driven, not cosmetic.
6. Test is a filter, not a formality
Every board passes 100% AOI and electrical test. A void in a via barrel can pass a continuity test at room temperature and fail after thermal cycling — which is why high-reliability orders get cross-sectioned coupons, and why the honest answer to "what tolerance did you actually hold?" is a coupon report, not a datasheet number.
What this means for your design
- Pin layer count and aspect ratio early — they drive cost more than anything after them.
- Assume inner-layer features are frozen once imaged; design the controlled impedance stackup before layout.
- If impedance is critical, specify test coupons; the report ships with the boards.